1. Field of the Invention
The invention relates to microcontrollers and computer systems, and more particularly to microcontrollers which need to select a clock from a variety of possible clock sources.
2. Description of the Related Art
Specialized microcontrollers with integrated communication features are becoming particularly attractive for communications applications. A microcontroller, or an embedded controller, is uniquely suited to combining functionality onto one monolithic semiconductor substrate (i.e. chip). By embedding various communication features within a single chip, a communications microcontroller may Support a wide range of communication applications.
Microcontrollers have been used for many years in many applications. A number of these applications involve communications over electronic networks, such as telephone lines, computer networks, and local and wide area networks, in both digital and analog formats. In communications applications, a microcontroller generally has a number of integrated communications peripherals in addition to the execution unit. These can be low and high speed serial ports, as well as more sophisticated communications peripherals, such as a universal serial bus (USB) interface, and high level data link control (HDLC) channels.
For high speed communications that use frames of data, HDLC channels are especially well suited. An HDLC channel transmits and receives frames based on the HDLC format. This format uses flags to determine the start and stop of a frame, and uses xe2x80x9cbit stuffingxe2x80x9d to maintain data transparency. An HDLC channel, however, is a general purpose device, and can be employed to implement a number of communications protocols, such as the general circuit interface (GCI) protocol (similar to an IOM-2 protocol) sometimes used for ISDN (integrated services digital network) communications (similar to the IOM-2 protocol), a pulse coded modulation (PCM) highway protocol, as well as raw data communications equipment (DCE) formats. These formats are synchronous communication protocols that may or may not include a separate clock.
But communications employing the HDLC format can be further implemented within time slots of a lower level time division multiplexed framing protocol, such as a T1 or E1 protocol. This protocol employs 24 or 32 time slots of 8 bits each, and each time slot could be used to carry different communications data, even in different formats. In such protocols, the time slots are determined based on a frame sync signal, which can be embedded in the data stream, be embedded in a clock stream, or even a separate signal, depending on the communications protocol. Each such time slot, for example, could be implemented to carry a separate HDLC channel of data.
Further, a time slot assigner (TSA) can be coupled in a microcontroller to an HDLC channel for slot-level placement of the HDLC data on the external communication path. Such a TSA determines the start of a programmed time slot relative to the frame sync. This could be to provide the HDLC data within a particular time slot, or to further implement some sort of protocol that employs its own time slots, such as the protocol used for ISDN. In the GCI protocol, a frame is subdivided into two 8-bit B channels and a 2-bit D channel, which form two separate 8-bit and one 2-bit xe2x80x9cslotxe2x80x9d within a communications frame on the GCI bus.
More generally, a time slot assigner (TSA) typically supports the isolation of 8-bit slots from 0 to 155 on a standard 8 kilohertz time division multiplexed (TDM) frame. This supports a variety of TDM buses, including GCI, E1, T1, PCM highway, and others. Of course, other length frames, other speeds, and other numbers of slots can be supported as well.
Support for multiple communications protocols has typically implied multiple clock sources are present. For a processor-based device, when a clock source from a number of clock sources must be selected for a clock line, clock glitches have commonly occurred on the clock line during switching of a clock source to the clock line. The timing of processor-based devices thus has been susceptible to such clock glitches. Clock behavior has been particularly critical for processor-based devices which support multiple data communication protocols such as those described above.
A clock switching technique for a processor-based device allows selecting an input clock signal from any number of clock sources. A clock mode signal controls a clock source selection logic which selects an input clock signal onto an output clock line. A clock invalid signal is asserted upon detection of a change in the clock mode signal. The clock invalid signal is deasserted after a predetermined number of output clock cycles. In this way, the clock invalid signal envelops the clock switching time during which a glitch may potentially be generated. The deasserted state of the clock invalid signal informs other circuitry in the processor-based device that an output clock line is stable and can be used.
The technique involves a clock mode change tracking logic and a synchronous clock invalid duration counter. The synchronous clock invalid duration counter counts output clock cycles and indicates to the clock mode change tracking logic that the predetermined number of output clock cycles have elapsed. The clock mode change tracking logic enables the synchronous clock invalid duration counter, causes the assertion of the clock invalid signal when the clock mode change tracking logic detects a change in the clock mode signal, disables and resets the synchronous clock invalid duration counter and causes the deassertion of the clock invalid signal upon being signaled by the synchronous clock invalid duration counter after reaching a predetermined number of output clock cycles. The internal clock line can be buffered, producing an output clock line.
In one embodiment, a clock mode switch delay logic delays the clock mode signal such that the clock invalid signal is asserted before switching a different input clock signal to the output clock line.
In one embodiment, asserting a reset signal causes the clock source selection logic to switch a default input clock signal to the output clock signal and the deassertion of the clock invalid signal.
In a further embodiment, the clock source selection logic can switch two of the input clock signals to two output clock signals, providing a transmit clock signal and a receive clock signal. In another embodiment, a second clock source selection logic can switch a second plurality of input clock signals to a third output clock signal synchronously with the first clock source selection logic. In one embodiment, an input clock signal can be an input clock signal to both the first clock source selection logic and the second clock source selection logic.
One advantage of this clock switching technique is that the circuit design is synchronous in nature and easy to implement. An unlimited number of clock sources can be switched using this technique. In a system that has many sources of clocks, this technique provides a flexible system, simplifying the design of the clock switching circuit. Another advantage is that clock switching is personnel on the fly and the clock switching is allowed to glitch onto the output clock line while protecting circuitries using the output clock signal through the use of the clock invalid signal. A further advantage is that the period of time after the clock source selection logic switch occurs can be scaled independently of the number of input clock sources. Further, the clock selection technique works independently of the frequency of any of the clock sources or system clock frequency.